SYSTEM DEVELOPERS CAN RAPIDLY EMBED IMAGE-PROCESSING ALGORITHMS USING FPGA PROGRAMMING TOOLS
08 July 2007 - Matrox VITE

To optimize image-processing algorithms most effectively, developers often tailor their algorithms in hardware description languages such as Verilog and VHDL.

Once described in this way, the programs can be compiled into register-transfer-logic net lists, synthesized into logical gates, then placed and routed and embedded into the FPGA.

For many, however, the task of programming in HDLs requires a steep learning curve and one that may add many months of labor to a machine-vision or image-processing design. Because of this, a number of companies are now offering image-processing libraries that run on FPGA-based boards that can eliminate programming in HDLs.

“Now,” says Reuven Weintraub, president and CTO of GiDEL, “the maturity of electronic-system-level design tools for FPGAs, coupled with demand for real-time performance in imaging and video-based applications, has turned designers to programmable logic to provide coprocessor acceleration for existing DSP or microprocessor solutions. Processor-intensive functions are offloaded to the FPGA, processed in real time, and returned to the host or migrated completely to the FPGA.”

Although these tools may not offer the ultimate performance of a finely tuned algorithm for a specific FPGA, they do offer a means for system developers to deploy code on FPGA-based frame grabbers and image-processing boards, while at the same time reducing possible time-to-market of the systems. Furthermore, because these tools provide a certain level of hardware abstraction, they do not require that the system’s developer understand the low-level timing and communications protocols between on-board hardware components. Rather, because such high-level interfaces have been developed on specific frame grabbers and image processors, they leverage the low-level drivers and application programming interfaces already developed by hardware vendors.

Silicon Software introduced a graphically oriented interface called VisualApplets that lets developers program machine-vision and image-processing functions on the company’s Xilinx Spartan IIe-based microEnable III PCI Camera Link frame grabber. Rather than use a VHDL compiler, these prewritten image-processing functions are transparently converted into an FPGA layout using Xilinx’s place and route software and then executed.

Using the PROC_HILs tool enables the developer to download the Simulink design into one of the company’s FPGA-based processing boards and simulate it, while the design runs on the on-board FPGAs, communicating with Simulink in real time. “By operating the added GiDEL PROC_HILs object to the design, an HDL code is automatically generated from the Simulink design and synthesized and compiled to an FPGA binary file that is compatible with the processing board,” says Weintraub.

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