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News

Wafer-bumping stencils maintain accuracy on 300mm format

Tecan : 06 June, 2003  (New Product)
In addition to the supply of standard wafer-bumping stencils, proven specialist Tecan is now producing stencils in the next-generation large format, of 300mm x 300mm (12in x 12in), while maintaining close tolerance and high resolution across the whole image. The ultra-accurate stencils are produced by electroforming, resulting in mirror-finish aperture walls, which ensure optimum solder paste release characteristics when depositing solder paste directly onto silicon wafer die.
The wafer-bumping stencils, or masks, cater for the increasingly high component densities and finer pitches associated with components such as chip-scale packages, micro ball-grid arrays (uBGAs) and flip-chip designs. For example, a typical stencil for a multi-die 150mm (six-inch) wafer may require 300,000 apertures, or over 500,000 for a 200mm (eight-inch) wafer. The 300mm x 300mm images may typically have in excess of two million apertures and hole diameters of 60 to 125 microns, in a 50 micron thick stencil.

For present-day and next-generation applications, the high-tolerance stencils allow users to significantly reduce defects and re-work while maximising the available yield from a given wafer, providing optimum results.

The company produces highly accurate mirror finish stencils which have apertures with exceptionally smooth side walls and a trapezoidal cross-section. Apertures of the dimensions highlighted are optimised using a combination of shape, with radiussed squares offering the best ratio of aperture base to wall. Refinements such as these ensure optimum paste release characteristics, for the finer ball pastes used in wafer-bumping, significantly improving the consistency of solder paste volume and regularity.

Process control is a fundamental element in the success of CSP, BGA and similar packaging. The adoption of Tecan electroformed stencils provides the ability to tightly control each assembly process to ensure repeatable high yields. The technology represents a significant step forward in the reduction of production costs for such increasingly miniaturised silicon substrate electronics components.

The following CAD formats are accepted, Gerber (RS274X), GWK, DPF and HPGL. All parts are produced within the company's strict ISO9002 quality-control regime.
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